Boolean expression for the output of the logic circuit shown in the figure is

1.  Y=AB+AB+C

2.  

3.  

4.  

View Answer  
4
Correct Answer :


Explanation :
No Explanation available for this question

For the circuit show in the figure below, what is the frequency of the output Q

1.  Twice the input clock frequency

2.  Half the input clock frequency

3.  Same as the input clock frequency

4.   Inverse of the propagation delay of the FF.

View Answer  
4
Correct Answer :

Half the input clock frequency


Explanation :
No Explanation available for this question

The following arrangement of master-slave flip flops has the initial state of P, Q as 0, 1 respectively. After three clock cycles, the output state P, Q respectively are

1.  1,0

2.  1,1

3.  0,0

4.  0,1.

View Answer  
4
Correct Answer :

1,0


Explanation :
No Explanation available for this question

The type of gate shown in the given figure is

1.  NOR

2.  OR

3.  NAND

4.  EX-OR.

View Answer  
4
Correct Answer :

EX-OR.


Explanation :
No Explanation available for this question

In the circuit of given figure, redundant gate is

1.  1

2.  2

3.  3

4.  4.

View Answer  
4
Correct Answer :

2


Explanation :
No Explanation available for this question

The input pulses to the different stages of the circuits shown in the following figure must be of

1.  Constant frequency and constant width

2.  Constant frequency bit variable width

3.  Variable frequency bit constant width

4.  Variable frequency as well as variable width.

View Answer  
4
Correct Answer :

Constant frequency bit variable width


Explanation :
No Explanation available for this question

The output y for the logic circuit shown in the figure is

1.  

2.  

3.  

4.  

View Answer  
4
Correct Answer :


Explanation :
No Explanation available for this question

The half adder circuit, in the given figure has inputs AB =11. The logic level of P and Q outputs will be

1.  P=0 and Q=0

2.  P=0 and Q=1

3.  P=1 and Q=0

4.  P=1 and Q=1.

View Answer  
4
Correct Answer :

P=0 and Q=1


Explanation :
No Explanation available for this question

For the comparator circuit shown in the figure. The forward diode voltage drop is V=0.7 V and reverse zener diode voltage is 5.6V. If hysteresis width is 1 V, then value of R2 is

1.  4kΩ

2.  12.6kΩ

3.  2kΩ

4.  6.3kΩ

View Answer  
4
Correct Answer :

12.6kΩ


Explanation :
No Explanation available for this question

Consider the regenerative comparator circuit shown in the figure. Two zener diodes are identical with Vz1=Vz2=Vz=4.6V. The voltage across conducting diode is 0.6V Upper threshold voltage is

1.  0.9912V

2.  1.0042V

3.  1.0094V

4.  0.9938V.

View Answer  
4
Correct Answer :

1.0042V


Explanation :
No Explanation available for this question
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