# Consider the regenerative comparator circuit shown in the figure. Two zener diodes are identical with Vz1=Vz2=Vz=4.6V. The voltage across conducting diode is 0.6V Lower threshold voltage is

1.  0.9932V

2.  0.9938V

3.  1.0012V

4.  1.0056V.

4

0.9938V

Explanation :
No Explanation available for this question

# For the digital circuit shown in figure, the output Q3Q2Q1Q0 =0001 initially. after a clock pulse appear, the output Q3Q2Q1Q0 will be

1.  0001

2.  0011

3.  0100

4.  1100.

4

0011

Explanation :
No Explanation available for this question

# The output QD of a J-K flip-flop is zero. It changes to 1 when a clock pulse is applied. The input PD and KD are respectively

1.  1 and X

2.  0 and X

3.  X and 0

4.  X and 1.

4

1 and X

Explanation :
No Explanation available for this question

# A memory has a total of 8 memory chips, each with 12 address lines and 4 data lines. The total size of the memory system is

1.  6 k bytes

2.  32 k bytes

3.  48 k bytes

4.  64 k bytes.

4

32 k bytes

Explanation :
No Explanation available for this question

# The Q output of a J-K flip-flop is ‘1’. The output does not change when a clock-pulse is applied. The inputs J and K will be respectively (X-denotes don’t care state)

1.  0 and X

2.  X and 0

3.  1 and 0

4.  0 and 1.

4

X and 0

Explanation :
No Explanation available for this question

# The block diagram shown below represents

1.  Modulo-3 ripple counter

2.  Modulo-5 ripple counter

3.  Modulo-7 ripple counter

4.  Modulo-7 synchronous counter.

4

Modulo-7 ripple counter

Explanation :
No Explanation available for this question

# A 4-bit preset table up counter has preset input 0101. The preset operation takes place as soon as the counter becomes maximum 1111. The modulus of the counter is

1.  5

2.  10

3.  11

4.  15.

4

10

Explanation :
No Explanation available for this question

# A mod-2 counter followed by a mod-5 counter is

1.  Same as a mode-5 counter followed by a mod-2 counter

3.  A mod-7 counter

4.  None of these.

4

Same as a mode-5 counter followed by a mod-2 counter

Explanation :
No Explanation available for this question

# A 4-bit synchronous counter uses flip-flops with propagation delay time of 25 ns each. The maximum possible time required for change of state will be

1.  25 ns

2.  50 ns

3.  75 ns

4.  100 ns.

4

25 ns

Explanation :
No Explanation available for this question

1.  SR flip-flop

2.  JK flip-flop

3.  D-FF

4.  T-FF.

4