# A  particular  green  LED  emits  light  of  wavelength  5490  Å.  The  energy  bandgap  of  the semiconductor material used there is (Planck's constant = 6.626 x 10-34 J-s)

1.  2.26 eV

2.  1.98 eV

3.  1.17 eV

4.  0.74 eV

4

2.26 eV

Explanation :
No Explanation available for this question

# When  the gate-to-source voltage (VGS) of a MOSFET with  threshold  voltage of 400 mV, working in saturation is 900 mV, the drain current in observed to be 1 mA. Neglecting the channel width modulation effect and assuming that the MOSFET is operating at saturation, the drain current for an applied VGS of 1400 mV is

1.  0.5 mA

2.  2.0 mA

3.  3.5 mA

4.  4.0 mA

4

4.0 mA

Explanation :
No Explanation available for this question

# If P  is Passivation, Q  is n-well  implant, R  is metallization and S  is  source/drain diffusion, then  the  order  in  which  they  are  carried  out  in  a  standard  n-well  CMOS  fabrication process, is

1.   P-Q-R-S

2.  Q-S-R-P

3.  R-P-S-Q

4.  S-R-Q-P

4

Q-S-R-P

Explanation :
No Explanation available for this question

# An  amplifier  without  feedback  has  a  voltage  gain  of  50,  input  resistance  of  1  K   and  output  resistance of 2.5 K ?. The  input  resistance of  the current-shunt negative  feedback amplifier using the above amplifier with a feedback factor of 0.2 is

1.  1/11 K

2.  1/5 K?

3.  5 K?

4.  11 K?

4

1/11 K

Explanation :
No Explanation available for this question

# In  the  amplifier  circuit  shown  in  the  figure  is the  values of R1  and R2  are  such  that  the transistor is operating at VCE = 3 V and IC = 1.5 mA when its β is 150. For a transistor with β of 200, the operating point (VCE, IC) is

1.  (2 V, 2 mA)

2.  (3 V, 2 mA)

3.  (4 V, 2 mA)

4.  (4 V, 1 mA)

4

(2 V, 2 mA)

Explanation :
No Explanation available for this question

# The oscillator circuit shown in the figure is has an ideal inverting amplifier. Its frequency of oscillation (in Hz) is

1.  1/(2π√(6) RC)

2.  1/(2π RC)

3.  1/(√(6) RC)

4.  1/(√(6)(2π RC))

4

1/(2π√(6) RC)

Explanation :
No Explanation available for this question

# The output voltage of the regulated power supply shown in the figure is

1.  3 V

2.  6 V

3.  9 V

4.  12 V

4

9 V

Explanation :
No Explanation available for this question

# The action of a JFET in its equivalent circuit can bast be represented as a

1.  Current Controlled Current Source

2.  Current Controlled Voltage Source

3.  Voltage Controlled Voltage Source

4.  Voltage Controlled Current Source

4

Voltage Controlled Current Source

Explanation :
No Explanation available for this question

# If the op-amp in the figure is idea, the output voltage Vout will be equal to

1.  1 V

2.  6 V

3.  14 V

4.  17 V

4

6 V

Explanation :
No Explanation available for this question

# A 4 bit ripple counter and a 4 bit synchronous counter are made using  flip  flops having apropagation  delay  of  10  ns  each.  If  the worst  case  delay  in  the  ripple  counter  and  the synchronous counter be R and S respectively, then

1.  R = 10 ns, S = 40 ns

2.  R = 40 ns, S = 10 ns

3.  R = 10 ns, S = 30 ns

4.  R = 30 ns, S = 10 ns

4

R = 40 ns, S = 10 ns

Explanation :
No Explanation available for this question

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