# Two systems H1(Z) and H2(Z) are connected in cascade as shown below. The overall output y(n) is the same as the input x(n) with a one unit delay. The transfer function of the second system H2(Z) is

1.  (1-0.6z-1)/z-1(1-0.4z-1)

2.  z-1 (1-0.6z-1)/z-1(1-0.4z-1)

3.   z-1 (1-0.4z-1)/z-1(1-0.6z-1)

4.  (1-0.4z-1)/z-1(1-0.6z-1)

4

z-1 (1-0.6z-1)/z-1(1-0.4z-1)

Explanation :
No Explanation available for this question

# Let y[n] denote the convolution of h[n] and g[n], where h[n], where h[n]=(1/2)n u[n] and g[n] is a casual sequence. If y[0]=1 and y[1]=1/2, then g[1] equals

1.   0

2.   ½

3.  1

4.  3/2

4

0

Explanation :
No Explanation available for this question

# A system  with the transfer function Y(s)/X(s)=s/s+p has an output y(t)=cos(2t-π/2). Then, the system parameter ‘p’ is

1.  √3

2.  2/√3

3.  1

4.  √3/2

4

2/√3

Explanation :
No Explanation available for this question

# Consider a memory chip with 1024 bytes storage connected to a 8085 chip address lines (or any microprocessor with 16 address lines) as shown below. What is the range of memory address

1.  0000 H to 03 FFH

2.  1000 H to 13 FFH

3.  F000 H to F3 FFH

4.  0000 H to FFFFH

4

1000 H to 13 FFH

Explanation :
No Explanation available for this question

# For the circuit shown below the counter state (Q1 Q0) follows the sequence

1.  00, 01, 10, 11, 00…

2.  00, 01, 10, 00, 01…

3.  00, 01, 11, 00, 01…

4.  00, 10, 11, 00, 10…

4

00, 01, 10, 00, 01…

Explanation :
No Explanation available for this question

# Analyze the sequential circuit shown above in figure. Assuming that initial state is 00, determine what input sequence would lead to state 11

1.  1 -1

2.  1 -0

3.  0 – 0

4.  State 11 is unreachable

4

0 – 0

Explanation :
No Explanation available for this question

# The shift register shown in the given figure is initially loaded with the bit pattern 1010. Subsequently the shift register is clocked, and with each clock pulse the pattern gets shifted by one bit position to the right. With each shift, the bit at the serial input is pushed to the msb position. After how many clock pulses will be content of the shift register become 1010 again

1.  3

2.  7

3.  11

4.  15

4

7

Explanation :
No Explanation available for this question

# For the logic circuit shown in the figure below, what is the required input condition (A, B, C) to make output X = 1

1.  1, 0, 1

2.  0, 0, 1

3.  1, 1, 1

4.  0, 1, 1

4

0, 1, 1

Explanation :
No Explanation available for this question

# The circuit is given below illustrates a typical application of the JK flip-flops. What does this represent

1.  A shift register

2.  A data storage device

3.  A frequency divider circuit

4.  A decoder circuit

4

A frequency divider circuit

Explanation :
No Explanation available for this question

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