# The circuit shown below is a

1.   J-K flip flop

2.  Johnsons counter

3.  R-S latch

4.  None of these

4

R-S latch

Explanation :
No Explanation available for this question

# The circuit shown in a figure is a

2.  Full subtractor

3.  Shift Register

4

Full subtractor

Explanation :
No Explanation available for this question

# The input x(t) and output y(t) of a system are related as . The system is

1.   Time-invariant and stable

2.  Stable and not time-invariant

3.  Time-invariant and not stable

4.  Not time-invariant and not stable

4

Not time-invariant and not stable

Explanation :
No Explanation available for this question

# In the circuit shown below the f- output is given by

1.  F=1

2.  F=0

3.  F=x

4.  F=2

4

F=0

Explanation :
No Explanation available for this question

# The impulse response of a continuous time system is given by h(t)=δ9t-1)+δ(t-3). The value of the step response at t=2 is

1.   0

2.  1

3.  2

4.  3

4

1

Explanation :
No Explanation available for this question

# Output voltage of a network shown in figure if digital output is 1011, is

1.  -3.875v

2.  -4.875V

3.  -5.875V

4.  -6.875V

4

-6.875V

Explanation :
No Explanation available for this question

# A system is defined by its impulse response h(n)=2n u(n-2). The system is

1.   Stable and causal

2.  Causal but not stable

3.  Stable but not causal

4.  Unstable and non causal

4

Causal but not stable

Explanation :
No Explanation available for this question

# The Circuit Shown in the given figure is a

1.  Positive logic OR circuit

2.  Negative logic OR gate

3.  Positive logic NAND gate

4.  Negative Logic NAND gate

4

Negative logic OR gate

Explanation :
No Explanation available for this question

# The transfer function of a discrete time LTI system is given by H(Z)=2-(3/4)z-1/1-(3/4)z-1+(1/8)z-2 Consider the following statements S1: The system is stable and causal for ROCKz|>1/2 S2: The system is stable but not causal for ROC: |z|

1.   Both S1 and S2 are true

2.  Both S2 and S3 are true

3.  Both S1 and S3 are true

4.  S1 , S2 and S3 are all true

4

Both S1 and S3 are true

Explanation :
No Explanation available for this question

1.  01011

2.  01010

3.  00110

4.  00101

4