# Consider the z-transform X9z)=5z2+4z-1+3; 0

1.   5 δ[n+2] + 3 δ[n]+4 δ[n-1]

2.  5 δ[n-2] + 3 δ[n]+4 δ[n+1]

3.   5 u[n+2] + 3 u[n]+4 u[n-1]

4.  5 δ[n-2] + 3 u[n]+4 u[n+1]

4

5 δ[n+2] + 3 δ[n]+4 δ[n-1]

Explanation :
No Explanation available for this question

# Consider the following logic circuit consisting of 2-4 decoder for each of decoder a. f0 = 1 when i1 = 0, i2 = 0 b. f1 = 1 when i1 = 1, i2 = 0 and so on which of the following gives value of f (x, y, z)

1.

2.  x. y. z

3.

4.  1

4

1

Explanation :
No Explanation available for this question

# If x[n]=(1/3)|n|-(1/2)nu[n], then the region of convergence (ROC) of its Z-transform in the Z-plane will be

1.   1/3

2.  1/3

3.  1/2

4.  1/3

4

1/2<|z|<3

Explanation :
No Explanation available for this question

# The combinational logic circuit shown in the given figure has an output Q which is

1.  A B C

2.  A + B + C

3.  A B ? C

4.  A ? B ? C

4

A + B + C

Explanation :
No Explanation available for this question

# The Z-transform of the following real expontial sequence x(nT)=an, nT≥0            =0, nT0 is given by

1.   (1/1-z-1); |z|>1

2.  (1/1-az-1); |z|>a

3.  1 for all z

4.  (1/1-az-1); |z|

4

(1/1-az-1); |z|>a

Explanation :
No Explanation available for this question

# The logic realized by the circuit shown in the figure below, is

1.  F = A C

2.  F = A ? C

3.  F = B ? C

4.  F = B ? C

4

F = A ? C

Explanation :
No Explanation available for this question

# The transfer function of a system is given by H9s)=1/s2(s-2). The impulse response of the system is

1.   (t2 * e-2t) U(t)

2.  (t * e2t) U(t)

3.  (t2 e-2t)U(t)

4.   (te-2t)U(t)

4

(t * e2t) U(t)

Explanation :
No Explanation available for this question

# In the figure shows a 4 to 1 MUX to be used to implement the sum S of a  1-bit full adder with input bits P and Q and the carry input Cin. Which of the following combinations of inputs to I0 , I1, I2  and I3 of the MUX will realize the sum S

1.

2.

3.

4.

4

Explanation :
No Explanation available for this question

# The output f of the 4-to-1 MUX shown in the given figure

1.  xy+ x

2.  x + y

3.  xy + y

4.  x2y

4

x + y

Explanation :
No Explanation available for this question

# In TTL circuit shown in the given figure, S2 to S0 are select line X7 to X0 are input lines S0 and X0 are LSB’s. The outputs y is

1.  In determine

2.  A B

3.

4.

4

Explanation :
No Explanation available for this question

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