# The circuit given below is that of a

1.  Mod-5 counter

2.  Mod-6 counter

3.  Mod-7 counter

4.  Mod-8 counter

4

Mod-5 counter

Explanation :
No Explanation available for this question

# 12 MHz clock frequency is applied to a cascaded counter of module-3 counter, modules-4 counter and modulus-5 counter. What are the lowest output frequency and the overall modulus, respectively

1.  2000 kHz, 60

2.  1 MHz, 60

3.  3 MHz, 12

4.  4 MHz, 12

4

2000 kHz, 60

Explanation :
No Explanation available for this question

# A 10-bit ADC with full-scale output voltage of 10.24 V is designed to have a + LSB/2 accuracy. If the ADC is calibrated at 250C and the operating temperature ranges from 00C to 500C, then the maximum net temperature coefficient of ADC should not exceed

1.  ±200 µV/0C

2.  ±400 µV/0C

3.  ±600 µV/0C

4.  ±800 µV/0C

4

±200 µV/0C

Explanation :
No Explanation available for this question

# In the circuit shown below Q1 has negligible collector-to-emitter saturation voltage and the diode drops negligible voltage across it under forward biased. If Vcc is +5V, X and Y are digital signals with 0V as logic 0 and Vcc as logic 1, then the Boolean expression for Z is

1.   XY

2.

3.

4.

4

Explanation :
No Explanation available for this question

# Which one of the following statements is not correct

1.  An 8 input MUX can be used to implement any 4 variable functions

2.  A 3 line to 8 line DEMUX can be used to implement any 4 variable function

3.  A 64 input MUX can be built nine 8 input MUXs

4.  A 6 line to 64 line DEMUX can be built using nine 3 line to 8 line DEMUXs

4

A 6 line to 64 line DEMUX can be built using nine 3 line to 8 line DEMUXs

Explanation :
No Explanation available for this question

# Digital multiplexer is basically a combinational logic circuit to perform the operation

1.  AND – AND

2.  OR – OR

3.  AND – OR

4.  OR – AND

4

AND – OR

Explanation :
No Explanation available for this question

# In time division multiplexing

1.  Time is double between bits of a byte

2.  Time slicing at CPU level takes place

3.  Total time available in the channel is divided between several users and each users is allotted at a time slice

4.  None of these

4

Total time available in the channel is divided between several users and each users is allotted at a time slice

Explanation :
No Explanation available for this question

# Which of the resistance networks of figure can be as 3 bit R-2R ladder DAC. Assume V0 corresponds to LSB

1.  Both (i) and (ii)

2.  Both (i) and (iii)

3.  Only (iii)

4.  Only (ii)

4

Only (iii)

Explanation :
No Explanation available for this question

# A sequential multiplexer is connected as shown in the figure. Each time the multiplexer receivers the clock, it switches to the next cannel (from 6 it goes to 1) if input signals are

1.  5 cos(2π)(4 x 103t)

2.  2 cos 2π(3.8 x 103 t)

3.  6 cos 2π(2.2 x 103 t)

4.  4 cos wπ(17 x 103 t)

4

4 cos wπ(17 x 103 t)

Explanation :
No Explanation available for this question

1.   2000H-20FFH

2.  2D00H-2DFFH

3.  2E00H-2EFFH

4.  FD00H-FDFFH

4