Circuit of DAC is given below. Switch are closed if input bit is 1, otherwise open.   If Vref = 5V, R = 20 KΩ, and RF = 10 kΩ, then full scale voltage is

1.  4.6875 V

2.  -4.6875 V

3.  5V

4.  -5V

View Answer  
4
Correct Answer :

-4.6875 V


Explanation :
No Explanation available for this question

An 8-bit digital – ramp ADc with a 40 mV resolution uses a clock frequency of 2.5 MHz and a comparator with VT = 1 mV. The digital output for VA = 6.000 V is

1.  10010111

2.  10010110

3.  1011110

4.  1011111

View Answer  
4
Correct Answer :

10010111


Explanation :
No Explanation available for this question

The circuit shown in the figure is a 4 – bit DAC. The input bits 0 and 1 are represented by 0 and 5 V respectively. The OP-AMP is ideal, but all the resistance and the 5V inputs have a tolerance of ± 10%. The specification (rounded to the  nearest multiple of 5%) for tolerance of the DAC is

1.  ± 35%

2.  ± 20%

3.  ± 10%

4.  ±5%

View Answer  
4
Correct Answer :

± 35\%


Explanation :
No Explanation available for this question

An Amplifier using an Op-Amp with a Slew –Rate SR = 1 V/μsec, has a gain of 40 dB. If this Amplifier has to faith fully Amplify sinusoidal signals from dc to 20 KHz. Without introducing any slew rate induced distortion, then the input signal level must npt exceed  

1.   795 mV

2.   395 mV

3.  79.5 mV

4.  39.5 mV

View Answer  
4
Correct Answer :

79.5 mV


Explanation :
No Explanation available for this question

PROMs are used to store

1.  Bulk information

2.  Sequential information

3.  Information to be accessed rarely

4.  Relatively permanent information

View Answer  
4
Correct Answer :

Information to be accessed rarely


Explanation :
No Explanation available for this question

Each cell of a static Random Access memory contains

1.  6 MOS transistors

2.  4 MOS transistors and 2 capacitors

3.  Two 2-input NORs and One X-NOR gate

4.  XOR gates and shift registers

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4
Correct Answer :

6 MOS transistors


Explanation :
No Explanation available for this question

The circuit shown is a

1.   Low pass filter with f3dB=(1/(R1+R2)C)rad/s

2.  High pass filter with f3dB=(1/R1C)rad/s

3.  Low pass filter with f3dB=(1/(R1)C)rad/s

4.  High pass filter with f3dB=(1/(R1+R2)C)rad/s

View Answer  
4
Correct Answer :

High pass filter with f3dB=(1/R1C)rad/s


Explanation :
No Explanation available for this question

Following sequence of instructions are executed by an 8085 microprocessor: 1000 L X I SP, 27 FF 10003 CALL 1006 1006 POP H Contents of the stack pointer (SP) and HL, register pair on completion of execution of these instructions are

1.  SP = 27 FF, hL = 1003

2.  SP = 27 FD, HL = 1003

3.  SP = 27 FF, HL = 1006

4.  SP = 27 FD, HL = 1006

View Answer  
4
Correct Answer :

SP = 27 FD, HL = 1006


Explanation :
No Explanation available for this question

A dynamic RAM call which hold 5V has to be refreshed every 20 m secs, so that stored voltage does not fall below 0.5V. If the call has a constant discharge current of 0.1 pA, then storage capacitance of the call is

1.  4 x 10-6

2.  4 x 10-9

3.  4 x 10-12

4.  4 x 10-15

View Answer  
4
Correct Answer :

4 x 10-15


Explanation :
No Explanation available for this question

In the circuit shown below the op-amps are ideal. Then Vout in Volts is

1.   4

2.  6

3.  8

4.  10

View Answer  
4
Correct Answer :

8


Explanation :
No Explanation available for this question
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