# Schmitt trigger is shown in the figure. The upper and lower threshold voltage are respectively

1.  2V, -4V

2.  2V, -2V

3.  4V, -4V

4.  4V, -2V

4

4V, -4V

Explanation :
No Explanation available for this question

# For a MOD -12 counter, FF has a tpd = 60 ns. NAND gate has a tpt of 25 ns. The clock frequency is

1.  =3.774 KHz

2.  >3.774 MHz

3.  < 3.774 MHz

4.  = 4.167 MHz

4

=3.774 KHz

Explanation :
No Explanation available for this question

# A sample and hold (S/H) circuit, having a holding capacitor of 0.1 nF, is used at the input of an ADC (analog-to-digita converte). The conversion time of the ADC is 1 μsec, and during this time the capacitor should bot lose more than 0.5% of the charge put across it during the sampling time. The maximum value of the input signal of the S/H circuit is 5V. The leakage current of the S/H circuit should be less than

1.  2.5 mA

2.  0.25 mA

3.  25.0 μA

4.  2.5 μA

4

2.5 μA

Explanation :
No Explanation available for this question

# The CMRR of the differential Amplifier of the fig is equal to

1.   ∞

2.  0

3.  900

4.  1800

4

Explanation :
No Explanation available for this question

# Among the following, the slowest ADC (Analog to-digical converter) is

1.   Parallel comparator (i.e, flash)type

2.  Successive approximation type

3.  Integrating type

4.  Counting type

4

Successive approximation type

Explanation :
No Explanation available for this question

# A 10 bit converter is used to digitsie in analog signal in the 0 to 5 V range. The maximum peak to peak ripple voltage that can be allowed in the d.c. supply voltage is

1.  Nearly 100 mV

2.  Nearly 50 mV

3.  Nearly 25 mV

4.  Nearly 5.0 mV

4

Nearly 5.0 mV

Explanation :
No Explanation available for this question

# The number of comparation in a parallel conversion type 8-bit A to D converter is

1.  8

2.  16

3.  255

4.  256

4

255

Explanation :
No Explanation available for this question

# An analog voltage is in the range of 0 to 8V is divided in eight equal intervals for conversion to 3-bit digital output. The maximum quantization error is

1.  0V

2.  0.5 V

3.  1 V

4.  2 V

4

1 V

Explanation :
No Explanation available for this question

# If resolution of a D/A converter is approximately 0.4% of its full scale range, then it is a/an

1.  8-bit converter

2.  10-bit converter

3.  12-bit converter

4.  16- bit converter

4

8-bit converter

Explanation :
No Explanation available for this question

# A 12-bit ADC is operating with a 1μ sec clock period and total conversion time is seen to be 14 μ secs. The ADC must to be of the

1.  lash type

2.  Counting type

3.  Integrating type

4.  Successive approximation type

4