# The transfer characteristic for the precision rectifier circuit  shown below is (assume ideal OP-AMP and practical diodes)

1.

2.

3.

4.

4

Explanation :
No Explanation available for this question

# A mod-2 counter followed by a mod-5 counter is

1.  Same as a mode-5 counter followed by a mod 2 counter

2.  a decade counter

3.  a mod-7 counter

4.   none of these

4

Same as a mode-5 counter followed by a mod 2 counter

Explanation :
No Explanation available for this question

# For the logic circuit shown in the figure, output Y is

1.  A B

2.

3.  A ? B ? C

4.  None of these

4

None of these

Explanation :
No Explanation available for this question

# A 4-bit synchronous counter uses flip-flops with propagation delay time of 25 ns each. The maximum possible time required for change of state will be

1.   25 ns

2.  50 ns

3.  75 ns

4.  100 ns

4

25 ns

Explanation :
No Explanation available for this question

# The circuit below implements a filter between the input current i1 and the output voltage v0. Assume that the op-amp is ideal. The filter implemented is a

1.   Low pass filter

2.  Band pass filter

3.  Band stop filter

4.  High pass filter

4

High pass filter

Explanation :
No Explanation available for this question

# The 8-to-1 multiplexer shown in the figure, realize which of the following Boolean expression

1.

2.

3.

4.  MUX is not enable

4

Explanation :
No Explanation available for this question

# A retriggerable monoshot is one which

1.  Can be triggered only once

2.  Has two quasi-stable states

3.  Cannot be triggered until full pulse has been

4.  Is capable of being triggered while the output is being

4

Is capable of being triggered while the output is being

Explanation :
No Explanation available for this question

# Part of a digital phase meter is shown in the given figure. IN put signals are VR(t) = VR sin ω t and VP (t) = - VP sin (ω t + 30°), then reading of the meter will be

1.  30°

2.  330°

3.  150°

4.  210°

4

210°

Explanation :
No Explanation available for this question

# In the circuit shown below what is the output voltage (Vout) if a silicon transistor Q and an ideal op-amp are used

1.   -15V

2.  -0.7V

3.   +0.7V

4.  +15 V

4

-0.7V

Explanation :
No Explanation available for this question

# A pulse train can be delayed by a finite number periods usings to clock

1.  A serial-in-serial shift register

2.  A serial-in-parallel-out shift register

3.  A parallel-n serial-out shift register

4.  A serial-in parallel-out shift register

4