The output F of the multiplexer circuit shown in the given figure can be represented by

1.  

2.  AB?C

3.  A ? B

4.  

View Answer  
4
Correct Answer :


Explanation :
No Explanation available for this question

In a JK flip –flop we have J = Q and K =1 Assuming the flip-flop was initially cleared and then clocked for 6 pulses , the sequence at the Q, then clock for the 6 pulses the sequence at the Q output will be

1.  010000

2.  011001

3.  010010

4.  010101

View Answer  
4
Correct Answer :

010101


Explanation :
No Explanation available for this question

A sequential multiplexer is connected as shown in the figure. Each time the multiplexer receivers the clock, it switches to the next cannel (from 6 it goes to 1) if input signals are

1.  5 cos(2π)(4 x 103t)

2.  2 cos 2π(3.8 x 103 t)

3.  6 cos 2π(2.2 x 103 t)

4.  4 cos wπ(17 x 103 t)

View Answer  
4
Correct Answer :

4 cos wπ(17 x 103 t)


Explanation :
No Explanation available for this question

A memory system has a total of 8 memory chips each with 12 address lines and 4 data lines. The total size of the memory system is

1.  6 kbytes

2.  32 kbytes

3.  48 kbytes

4.  64 kbytes

View Answer  
4
Correct Answer :

32 kbytes


Explanation :
No Explanation available for this question

The value of Z1 is

1.  a+b+c

2.  ab + ac + bc

3.  a b ? c

4.  a ? b ? c

View Answer  
4
Correct Answer :

a ? b ? c


Explanation :
No Explanation available for this question

Assuming the Op-AMP to be ideal, the voltage gain of the amplifier shown below is

1.   –(R2/R1)

2.  –(R3/R1)

3.  –((R2 || R3)/R1)

4.   –(R2+R3/R1)

View Answer  
4
Correct Answer :

–(R2/R1)


Explanation :
No Explanation available for this question

The Q output of a J-K flip-flop is ‘1’ . The output does not change when a clock-pulse is applied. The inputs J and K will be respectively (X-denotes don’t care state)

1.  0 and X

2.  X and 0

3.  1 and 0

4.  0 and 1

View Answer  
4
Correct Answer :

X and 0


Explanation :
No Explanation available for this question

The circuit act as a

1.  Full adder

2.  Half adder

3.  Full subtractor

4.  Half subtractor

View Answer  
4
Correct Answer :

Full adder


Explanation :
No Explanation available for this question

The block diagram shown below represents

1.  Modulo – 3 ripple counter

2.  Modulo – 5 ripple counter

3.  Modulo – 7 ripple counter

4.  Modulo – 7 synchronous counter

View Answer  
4
Correct Answer :

Modulo – 7 ripple counter


Explanation :
No Explanation available for this question

The ouput of the 4 x 1 multiplexer shown in the figure, is

1.  X + Y

2.  

3.  

4.  

View Answer  
4
Correct Answer :

X + Y


Explanation :
No Explanation available for this question
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