# For the CMOS inverter circuit shown below assume that both the transistors are in saturation then the voltage gain (v0/vin) is

1.

2.

3.

4.

4

Explanation :
No Explanation available for this question

# Consider a voltage follower is to be implemented with op.amp having rd = 1KΩ, ro = 20KΩ and a = 106V/V [poor resistance, but excellent gain]. Then what is the closed loop gain Af, input resistance, (Rin) and output resistance (R0) of the voltage follower.

1.  Af = 0.9999, Rin = 1MΩ R0 = 2KΩ

2.  Af = 0.9999, Rin = 1GΩ R0 = 20KΩ

3.  Af = 0.9999, Rin = 1GΩ R0 = 20mΩ

4.  Af = 1

4

Af = 0.9999, Rin = 1GΩ R0 = 20mΩ

Explanation :
No Explanation available for this question

# A non inverting amplifier is implemented with two 10 KΩ resistances having 5% tolerance. Then the range of possible values of gain A is

1.  1.9 V/V→2.1V/V

2.  1V/V→2 V/V

3.   2.1 V/V → 2.4 V/V

4.  1.5 V/ V → 2.5 V/V

4

1.9 V/V→2.1V/V

Explanation :
No Explanation available for this question

# For the MOS CASCODE amplifier circuit shown below, both the transistors are in saturation. If the current source is ideal then voltage gain of this amplifier is

1.

2.

3.

4.

4

Explanation :
No Explanation available for this question

# An n-channel JFET, having a pinch off voltage of -5V shows a Trans conductance (gm) of 1 mA/V. When the applied Gate to source voltage is -3V, it’s maximum trans conductance is (in mA/V)

1.  1.5

2.  2.0

3.  2.5

4.  3.0

4

2.5

Explanation :
No Explanation available for this question

# If the differential Voltage gain and common mode voltage gain of a differential amplifier are 48dB and 2dB respectively, then its common mode rejection ration is

1.  23dB

2.  25dB

3.  46dB

4.  50dB

4

46dB

Explanation :
No Explanation available for this question

# The action of a JFET in it’s equivalent circuit can be represented as a

1.  Current controlled current source

2.  Current controlled voltage source

3.  Voltage controlled voltage source

4.  Voltage controlled current source

4

Voltage controlled current source

Explanation :
No Explanation available for this question

# The voltage gain AV = v0/vin of the JFET amplifier shown below is ISS = 10mA, Vp = -5V, (Assume C1, C2, C3 to be very large)

1.  +18 V/V

2.  -18 V/V

3.  +6 V/V

4.  -6 V/V

4

-6 V/V

Explanation :
No Explanation available for this question

# An operational amplifier possessor

1.  Very large input resistance & very large output resistance

2.  Very small input resistance & very small output resistance

3.  Very large input resistance & very small output resistance

4.  Very small input resistance & very small output resistance

4

Very large input resistance & very small output resistance

Explanation :
No Explanation available for this question

# A non inverting amplifier of figure shown in below is implemented with R1 = 10 KΩ, R2 = 15 KΩ, and a 741 op.amp powered from 12V supply, if the circuit includes a third 30 KΩ resistor connected between the inverting terminal and the +12V supply. Find V0 & VN if V1 = 4V

1.  V0 = 6V, VN = 4V

2.  V0 = 10V, VN = 6V

3.   V0 =1= 6V, VN = 10V

4.  V0 = 4V, VN = 6V

4