1.
2.
3.
4.
1. 0.1
2. 0.9
3. 1.0
4. 9.0
9.0
1.
2.
3.
4.
1. The multi-emitter input stage
2. The phase-splitter
3. The output buffer
4. Open collector output stage
The output buffer
1. 1 and 3 are correct
2. 1 and 2 are correct
3. 2 and 4 are correct
4. 3 and 4 are correct
2 and 4 are correct
1. Are retarded
2. Are accelerated
3. Remains unaffected
4. None of the above
Are accelerated
1. 6 MDS transistors
2. 4 MOS transistors and 2 capacitors
3. Two 2-input NORs and One X-NOR gate
4. XOR gates and shift registers
6 MDS transistors
1. Totally retarded
2. Retarded
3. Accelerated
4. Neither accelerated nor retarded
Retarded
1. V0/Ts2 + V0/Ts2 e-St
2. V0/Ts2 – V0/Ts2 e-St
3. V0/Ts2 – V0/Ts e-St
4. V0/Ts2 + V0/Ts2 e-St(1+St)
V0/Ts2 + V0/Ts2 e-St(1+St)
1. Lower voltage gain
2. Higher voltage gain
3. Faster drop in filter response
4. Higher-cut-off frequency
Faster drop in filter response