In the program below, the number of times the FIRST and SECOND JNZ instructions cause the control to be transferred to LOOP respectively MVI H, 02 H MVI L, 05 H LOOP: DCR L FIRST: JNZ LOOP DLR H SECOND: JNZ LOOP

1.  5 and 2

2.  4 and 1

3.  259 and 1

4.  260 and 1

View Answer  
4
Correct Answer :

259 and 1


Explanation :
No Explanation available for this question

Which of the following demodulator (s) can be used for demodulating the signal S(t) = 5 (1 +2 cos 2000 π t) cos 2000 π t.

1.  Envelope demodulator

2.  Square-law demodulator

3.   Synchronous demodulator

4.  None of these

View Answer  
4
Correct Answer :

Synchronous demodulator


Explanation :
No Explanation available for this question

A switch-tail ring counter is made by using a single D FF. The resulting circuit is

1.  SR flip-flop

2.  JK flip-flop

3.  D-FF

4.  T-FF

View Answer  
4
Correct Answer :

D-FF


Explanation :
No Explanation available for this question

A super heterodyne ratio receiver with an intermediate frequency of 455 KHz is turned to a station operating at 1200 KHz. The associated image frequency is

1.  55 KHz

2.  1110 KHz

3.  2110 KHz

4.  4220 KHz

View Answer  
4
Correct Answer :

2110 KHz


Explanation :
No Explanation available for this question

A 4-bit modulo-16 ripple counter used JK flip-flop. If the progression delay of each FF is 50 ms, the maximum clock frequency is equal to

1.  20 M H Z

2.  10 M H Z

3.  5 M H Z

4.  4 M H Z

View Answer  
4
Correct Answer :

5 M H Z


Explanation :
No Explanation available for this question

Six independent low pass signals of bandwidth 3 W, W, W, 2W, 3W and 2W Hz are to be time-division-multiplexer on a common channel using PAM. To achieve this, the minimum transmission bandwidth of the channel should be…….Hz

1.  3 W

2.  6 W

3.  12 W

4.  24 W

View Answer  
4
Correct Answer :

12 W


Explanation :
No Explanation available for this question

A 12-bit ADC is operating with a 1μ sec to be 14 μ secs. The ADC must to be of the

1.  flash type

2.  counting type

3.  integrating type

4.  successive approximation type

View Answer  
4
Correct Answer :

successive approximation type


Explanation :
No Explanation available for this question

A pulse train can be delayed by a finite number periods using of clock

1.  a serial- in-serial shift register

2.  a serial-in-parallel-out shift register

3.  a parallel-in serial-out shift register

4.  a serial-in serial-out shift register

View Answer  
4
Correct Answer :

a serial- in-serial shift register


Explanation :
No Explanation available for this question

Match each of the items A, B and C with an appropriate item from 1, 2, 3, 4 and 5 A. Single side band B. Amplitude modulation C. Binary phase shift keying 1. Envelop detector 2. Integrate and dump 3. Hilbert and dump 4. Ratio detector 5. Phase locked loop

1.  A-1, B-2, C-3

2.  A-2, B-4, C-5

3.  A-3, B-1, C-5

4.   A-4, B-2, C-1

View Answer  
4
Correct Answer :

A-3, B-1, C-5


Explanation :
No Explanation available for this question

The minimum number of NAND gates required to implementis equal to

1.  zero

2.  1

3.  4

4.  7

View Answer  
4
Correct Answer :

zero


Explanation :
No Explanation available for this question
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