# A carrier is frequency modulated with a Quisoidal of 2 KHz resulting in a maximum frequency duration of 5 KHZ, then the bandwidth of the modulated signal will be

1.   7 KHz

2.  10 KHz

3.  14 KHz

4.  4 KHz

5.  3000

6.  4000

7.  3500

8.  2500

8

2500

Explanation :
No Explanation available for this question

# The number of comparators in a parallel conversion type 8- bit A to D converier is

1.  8

2.  16

3.  255

4.  255

4

255

Explanation :
No Explanation available for this question

# The position and acceleration error coefficients for the open-loop transfer function respectively are

1.  Zero and infinity

2.   Infinity and Zero

3.  (k/100) and zero

4.  Infinity and k/1000

4

Infinity and k/1000

Explanation :
No Explanation available for this question

# A DSB-SC signal is generated using the carrier cos (ω0 t + θ) and modulating signal x (t). The envelop of the DSB-SC signal is

1.  x(t)

2.

3.  Only positive portion of x(t)

4.  x(t) cosθ

5.  2000

6.  1200

7.  600

8.  12000

8

12000

Explanation :
No Explanation available for this question

# For the digital circuit shown in figure, the output Q3Q2Q1Q0 = 0001 initially. After a clock pulse appear, the output Q3Q2Q1Q0 will be

1.  0001

2.  0011

3.  0100

4.  1100

4

0011

Explanation :
No Explanation available for this question

# If the negative logic is used, the diode gate shown in the given figure will represent

1.  OR gate.

2.  AND gate

3.  NOR gate

4.  NAND gate

4

AND gate

Explanation :
No Explanation available for this question

# The input to a matched filter is given bythe peak amplitude of the filter output is

1.   10 volts

2.  5 volts

3.  10 mill volts

4.  5 mill volts

4

10 volts

Explanation :
No Explanation available for this question

# The position and velocity error co-efficient for the system of transfer function

1.   zero and zero

2.   zero and infinity

3.   50 and zero

4.  50 and infinity

5.  178

6.  204

7.  195

8.  488

8

204

Explanation :
No Explanation available for this question

# Which of the following is the truth table of the given logic is true

1.   X Y z 0 0 1 1 0 1 0 1 1 1 1 1

2.   X Y z 0 0 1 1 0 1 0 1 0 1 1 1

3.   X Y z 0 0 1 1 0 1 0 1 1 0 0 0

4.   X Y z 0 0 1 1 0 1 0 1 0 1 1 0

4
 X Y z 0 0 1 1 0 1 0 1 1 1 1 1

Explanation :
No Explanation available for this question

1.

2.

3.

4.

4