# Natural frequency of a unity feedback control system of transfer function G(s) = (10/s(s+1))  is

4.  None of these

4

Explanation :
No Explanation available for this question

# The Boolean expression for the output of the logic circuit shown in the figure is

1.  Y = AB + AB + C

2.

3.

4.

4

Explanation :
No Explanation available for this question

# Which of the following demodulator can be used for demodulating the signal X(t) = 5(1 + 2 cos 2000π t) cos 2000 π t

1.  Envelop demodulator

2.  Square-law demodulator

3.  Synchronous demodulator

4.  None of these

4

Square-law demodulator

Explanation :
No Explanation available for this question

# The number of comparisons carried out in a 4 bit flash-type A/D converter is

1.  16

2.  15

3.  4

4.  4

4

15

Explanation :
No Explanation available for this question

# An AWGN channel with 4 KHz bandwidth and noise power spectral density n/2 = 10-12 W/Hz. The signal power required at the receiver is 0.1 mW. The capacity of the channel will be

1.  54.44 Kb/sec

2.  8 Kb/sec

3.  64.44 Kb/sec

4.  34.32 Kb/sec

4

54.44 Kb/sec

Explanation :
No Explanation available for this question

1.   60%

2.   40%

3.  20%

4.  10%

4

40\%

Explanation :
No Explanation available for this question

# A 10 bit A/D converter is used to digitize an analog signal in the 0 to 5 V range. The maximum peak to peak ripple voltage that can be allowed in the d. c. supply voltage is

1.  nearly 100 mV

2.  nearly 50 mV

3.  nearly 25 mV

4.  nearly 5.0 mV

4

nearly 5.0 mV

Explanation :
No Explanation available for this question

# Which of the following can be achieved by using the reset terminals in a tuner chip

1.  Keyed oscillations

2.  Delayed mono stable

3.  square wave generation

4.  Pulse generation

4

Pulse generation

Explanation :
No Explanation available for this question

# Given an angle modulated signal then the frequency deviation will be

1.   5 KHz

2.  1 KHz

3.  2 KHz

4.  10 KHz

4

5 KHz

Explanation :
No Explanation available for this question

# The switching circuit given in the figure can be expressed in binary logic notation as

1.  L = (A+B) (C+D) E

2.  L = AB + CD + E

3.  L = E + (A+B) (C+D)

4.  L = (AB+CD) E

4