The state transition diagram for the logic circuit shown is

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The full forms of the abbreviations TTL and CMOS in reference to logic families are 1.     The full forms of  the abbreviations TTL and CMOS in reference to logic families are a.     Triple transistor logic and chip metal oxide semiconductor b.    Tristate transistor logic and chip metal oxide semiconductor c.     Transistor logic and complementary metal oxide semiconductor d.    Tristate transistor logic and complementary metal oxide silicon Ans.c

1.  Triple transistor logic and chip metal oxide semiconductor

2.  Tristate transistor logic and chip metal oxide semiconductor

3.  Transistor logic and complementary metal oxide semiconductor

4.  Tristate transistor logic and complementary metal oxide silicon

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Correct Answer :

Transistor logic and complementary metal oxide semiconductor


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A PLA realization is shown in the figure. f1 (x2,x1,x0) will be

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An X-Y flip-flop, whose characteristic table is given below, is to be implemented using J-K flip-flop. This can be done by making

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The circuit shown below is to be used to implement the function What values are to be selected for I and J

1.  I=0 ,J=B

2.  I=A, J=B

3.  I=B, J=1

4.  I=B, J=0.

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Correct Answer :

I=B, J=1


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Consider the following J-K flip flop: In the given J-K flip-flop J= and K=1. Assume that the flip-flop was initially cleared and then clocked for 6 pulses. What is the sequence at the Q output

1.  010000

2.  011001

3.  010010

4.  010101.

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Correct Answer :

010101.


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For the circuit shown in the following figure, I0-I3 are inputs to the 4:1 multiplexer. R(MSB) and S are control bits. The output Z can be represented by

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For each of the positive edge-triggered J.K flop used in the following figure, the propagate delay is T. Which of the following waveforms correct represents the output at Q1?

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Explanation :
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If X=1 in the logic equation Then

1.  Y=Z

2.  

3.  Z=1

4.  Z=0.

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Correct Answer :

Z=0.


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Two D flip-flop are connected as a synchronous counter that goes through the following QB QA SEQUENCE 00→11→01→10→00→… The connection to the inputs DA and DB are

1.  DA= QB, DB= QA

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Explanation :
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