# For the circuit shown in the figure below, what is the frequency of the output Q

1.  Twice the input clock frequency

2.  Half the input clock frequency

3.  Same as the input clock frequency

4.  Inverse of the propagation delay of the FF.

4

Half the input clock frequency

Explanation :
No Explanation available for this question

# Which one of the following logic operations performed by the digital circuit shown below

1.  NOR

2.  NAND

3.  X-OR

4.  OR.

4

X-OR

Explanation :
No Explanation available for this question

# In the circuit given below, both transistors have the same VT. what is the approximate value of the highest possible output voltage Vout, if Vin can range from 0 to VDD(assume 0

1.  VDD-VT

2.  VDD

3.  VT

4.  0.

4

VDD-VT

Explanation :
No Explanation available for this question

# Consider the following statements: A4:16 decoder can be constructed (with enable input by) Using four 2:4 decoders (each with an one input) only Using five 2:4 decoders (each with an one input) only Using two 3:8 decoders (each with an one input) only Using two 3:8 decoders (each with an one input) and an inverter. Which of the statements given above is/are correct

1.  2 and 3

2.  1 only

3.  2 and 4

4.  None of these.

4

2 and 4

Explanation :
No Explanation available for this question

# The circuit given below is that of a

1.  Mod-5 counter

2.  Mod-6 counter

3.  Mod-7 counter

4.  Mod-8 counter.

4

Mod-5 counter

Explanation :
No Explanation available for this question

# 12 MHz clock frequency is applied to a cascade counter of modules-3 counter, modules-4 counter and modules-5 counter. What are the lower output frequency and the overall modules respectively

1.  200 kHz

2.  1MHz, 60

3.  3MHz, 12

4.  4MHz, 12.

4

200 kHz

Explanation :
No Explanation available for this question

# The minimized expression for the given K-map(A: don’t care) is

1.  A+BC

2.  B+AC

3.  C+AB

4.  ABC.

4

A+BC

Explanation :
No Explanation available for this question

# A 10 bit ADC with full-scale output voltage of 10.24 V is designed to have a + LSB/2 accuracy. If the ADC is calibrated at 250 C and the operating temperature ranges from 00 to 500C, then the maximum net temperature coefficient of ADC should at exceed

1.  ±200µV/0C

2.  ±400µV/0C

3.  ±600µV/0C

4.  ±800µV/0C

4

±200µV/0C

Explanation :
No Explanation available for this question

# Which one of the following statements is not correct

1.  An 8 input MUX can be used to implement any 4 variable function

2.  A 3 line to 8 line DEMUX can be used to implement any 4 variable function

3.  A 64 input MUX can be built nine 8 input MUXs

4.  A 6 line to 64 line DEMUX can be built using nine 3 line to 8 line DEMUXs.

4

A 6 line to 64 line DEMUX can be built using nine 3 line to 8 line DEMUXs.

Explanation :
No Explanation available for this question

1.  P NOR Q

2.  P NAND Q

3.  P OR Q

4.  P AND Q

4