# The J-K flip-flop shown below is initially reset so that Q=0. If a sequence of four clock pulse is then applied, with the J and K inputs as given in the figure, the resulting sequence of value that appear at the output Q starting with the initial state, is given by

1.  01011

2.  01010

3.  00110

4.  00101.

4

00101.

Explanation :
No Explanation available for this question

# Consider a memory chip with 1024 bytes storage connected to a 8085 chip address lines (or any microprocessor with 16 address lines) as shown below. What is the range of memory address

1.  0000H to 03FFH

2.  1000H to 13FFH

3.  F000H to F3FFH

4.  0000H to FFFFH.

4

1000H to 13FFH

Explanation :
No Explanation available for this question

# For the circuit shown below the counter state (Q1, Q0) follows the sequence

1.  00, 01, 10, 11, 00…………

2.  00, 01, 10, 00, 01………..

3.  00, 01, 11, 00, 01………..

4.  00, 10, 11, 00, 10………

4

00, 01, 10, 00, 01………..

Explanation :
No Explanation available for this question

# Analyze the sequential circuit shown above in figure. Assuming that the initial state is 00, determine what input sequence would lead to state 11

1.  1-1

2.  1-0

3.  0-0

4.  State 11 is unreachable.

4

0-0

Explanation :
No Explanation available for this question

# The shift register shown in the given figure is initially loaded with the bit pattern 1010. Subsequently the shift register is clocked, and with each clock pulse the pattern gets shifted by one bit position to the right. With each shift, the bit at the serial input is pushed to the msb position. After how many clock pulses will be content of the shift register become 1010 again

1.  3

2.  7

3.  11

4.  15

4

7

Explanation :
No Explanation available for this question

# The Boolean functions can be expressed in canonical SOP(sum of products) and POS(products of sums) form. For the function, which are such two forms

1.  Y=Σ(1,2,6,7) and y=∏(0, 2, 4)

2.  Y=Σ(1,4,5,6,7) and y=∏(0, 2, 3)

3.  Y=Σ(1,2,5,6,7) and y=∏(0, 1, 3)

4.  Y=Σ(1,2,4,5,6,7) and y=∏(0, 2, 3, 4).

4

Y=Σ(1,4,5,6,7) and y=∏(0, 2, 3)

Explanation :
No Explanation available for this question

# For the logic circuit shown in the figure below, what is the required input condition (A, B, C) to make output X=1

1.  1, 0, 1

2.  0, 0, 1

3.  1, 1, 1

4.  0, 1, 1

4

0, 1, 1

Explanation :
No Explanation available for this question

# The circuit is given below illustrates a typical application of the J-K flip-flops. What does this represent

1.  A shift register

2.  A data storage device

3.  A frequency divider circuit

4.  A decoder circuit.

4

A frequency divider circuit

Explanation :
No Explanation available for this question

# The figure given below shows the circuit of which one of the following is

1.  Bi-stable multi-vibrator

2.  Schmitt trigger

3.  Mono-stable multi-vibrator

4.  A stable multi-vibrator.

4

Mono-stable multi-vibrator

Explanation :
No Explanation available for this question

# The black box in the figure below, consists of a minimum complexity circuit that uses only AND, OR, and NOT gates The function f(x, y, z)=1 whenever x, y are different and 0 otherwise. In addition the 3 inputs x, y, z are never all the same value Which one of the following equations leads to the correct design for the minimum complexity circuit

1.  x’ y + x y’

2.  x+ y z’

3.  x’ y’ z + x y’ z

4.  x y + y’ z + z’.

4