# In the circuit shown, the output will be

1.  Sine wave

2.  Square wave pulse

3.  Linear

4.  Non-linear.

4

Square wave pulse

Explanation :
No Explanation available for this question

# The circuit shown below is a

1.  J-K flip flop

2.  Johnson’s counter

3.  R-S latch

4.  None of these.

4

R-S latch

Explanation :
No Explanation available for this question

# The circuit shown in the figure is a

2.  Full sub tractor

3.  Shift register

4

Full sub tractor

Explanation :
No Explanation available for this question

# In the circuit shown below the F output is given by

1.  F=1

2.  F=0

3.  F=x

4.  F=2.

4

F=0

Explanation :
No Explanation available for this question

# Output voltage of a network shown in figure if digital input is 1011, is

1.  -3.875V

2.  -4.875V

3.  -5.875V

4.  -6.875V.

4

-6.875V.

Explanation :
No Explanation available for this question

# The circuit shown in the given figure is a

1.  Positive logic OR circuit

2.  Negative logic OR gate

3.  Positive logic NAND gate

4.  Negative logic NAND gate.

4

Negative logic OR gate

Explanation :
No Explanation available for this question

# J-K flip flop shown in figure is initially reset so that Q=0. A sequence of four clock pulses is, then applied, with the J and K inputs, as given in the figure, resulting sequence of values that the output Q will have, is given by

1.  01011

2.  01010

3.  00110

4.  00101.

4

01010

Explanation :
No Explanation available for this question

# Which of the following statements are correct

1.  A flip-flop is used to store 1 bit of information

2.  Race-around condition occurs in a J-K flip-flop when both the inputs are 1

3.  A transparent latch consists of a D-type flip-flop

4.  All of these.

4

All of these.

Explanation :
No Explanation available for this question

# Contents of accumulator after execution of following instructions will be MVI A, A7H ORA A RLC

1.  CFH

2.  4FH

3.  4EH

4.  CEH

4

4FH

Explanation :
No Explanation available for this question

# Which of the following condition, clocked J-K flip-flop can be used as a divide-by-2 circuit when input signal is applied at clock input

1.  J=K=1 and flip-flop has active high inputs

2.  J=K=0 and flip-flop has active low inputs

3.  J=K=1 and flip-flop active low inputs

4.  J=K=1 and flip-flop should be negative edge triggered.

4