1.  0000 H to FFFF H

2.  0000 H to 5FFF H

3.  4000 H to 5FFFF H

4.  3000 H to FFFF H.

4
Correct Answer :

0000 H to 5FFF H


Explanation :
No Explanation available for this question

1.  8-bit register in the microprocessor

2.  16-bit register in the microprocessor

3.  Set of memory locations in R/W memory reserved for sorting information temporarily during the execution of a program

4.  16-bit memory address stored in the program counter.

4
Correct Answer :

Set of memory locations in R/W memory reserved for sorting information temporarily during the execution of a program


Explanation :
No Explanation available for this question

1.  Bytes from 51H to 82H at PORT2

2.  00H AT PORT1

3.  All byte at PORT1

4.  Bytes from 52H to 81H at PORT2

4
Correct Answer :

Bytes from 51H to 82H at PORT2


Explanation :
No Explanation available for this question

1.  Output of 87H at PORT1

2.  Output of 87H at PORT2

3.  Infinite looping of the program execution with accumulator data alternating at 00H

4.  Infinite looping of the program execution with accumulator data alternating between 00H and 87H.

4
Correct Answer :

Output of 87H at PORT2


Explanation :
No Explanation available for this question

1.  A7H

2.  98H

3.  47H

4.  None of these.

4
Correct Answer :

A7H


Explanation :
No Explanation available for this question

1.  Gray code number

2.  2-4-2-1 BCD number

3.  Excess 3 code converter

4.  None of these.

4
Correct Answer :

2-4-2-1 BCD number


Explanation :
No Explanation available for this question

1.  1 times

2.  8 times

3.  7 times

4.  Infinite times

4
Correct Answer :

1 times


Explanation :
No Explanation available for this question

1.  The microprocessor is disconnected form the system bus till the reset is pressed

2.  The microprocessor enters into a halt state and the buses are tri-stated

3.  The microprocessor reloads the program from the locations 0024 and 0025H

4.  The microprocessor halts execution of the program and returns to monitor

4
Correct Answer :

The microprocessor enters into a halt state and the buses are tri-stated


Explanation :
No Explanation available for this question

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