# The circuit shown in the figure is a 4-bit DAC, if input bits 0 and 1 are represented by 0 and 1 respectively. The OP-AMP is ideal, but all resistance and the 5v inputs have tolerance of 10%. The specification (rounded to the near multiple of 5%) for tolerance of the DAC is

1.  ±35%

2.  ±20%

3.  ±10%

4.  ±5%

4

±35\%

Explanation :
No Explanation available for this question

# PROMs are used to store

1.  Bulk information

2.  Sequential information

3.  Information to be accessed rarely

4.  Relatively permanent information.

4

Information to be accessed rarely

Explanation :
No Explanation available for this question

# Each cell of a static random access memory contains

1.  6 MOS transistors

2.  4 MOS transistors and 2 capacitors

3.  Two 2- input NORs and One X-NOR gate

4.  XOR gates and shift registers.

4

6 MOS transistors

Explanation :
No Explanation available for this question

# The decoding circuit has been used to generate the active low chip. Then signal for a microprocessor peripheral is (address line are designed as A0 to A7 for I/O address)

1.  60H to 63H

2.  A4 to A7H

3.  70H to 73H

4.  70H to 73H

4

60H to 63H

Explanation :
No Explanation available for this question

# Following sequence of instructions are executed by an 8085 microprocessor: 1000 LXI SP, 27FF 1003 CALL 1006 1006 POP H Contents of the stack pointer (SP) and HL, register pair on completion of execution of these instructions are

1.  SP=27 FF, HL=1003

2.  SP=27 FD, HL=1003

3.  SP=27 FF, HL=1006

4.  SP=27 FD, HL=1006.

4

SP=27 FD, HL=1006.

Explanation :
No Explanation available for this question

# A dynamic RAM call which holds 5v has to be refreshed every 20 m secs, so that stored voltage does not fall below 0.5V. if the call has a constant discharge current of 0.1 pA, then storage capacitance of the call is

1.  4×10-6

2.  4×10-9

3.  4×10-12

4.  4×10-15

4

4×10-15

Explanation :
No Explanation available for this question

# The data-bus width of a 204 x 8 bits is

1.  8

2.  10

3.  12

4.  16

4

8

Explanation :
No Explanation available for this question

# Four memory clips of 16 x 4 size have their address bases connected together. The system will be of size

1.  64×64

2.  16×16

3.  32×8

4.  256×1

4

16×16

Explanation :
No Explanation available for this question

# In the program below, the number of times the first and second Jnz instructions cause the control to be transferred to loop are respectively MVI H, 02H MVI L, 05H LOOP: DCR L FIRST: JNZ LOOP DLR H SECOND: JNZ LOOP

1.  5 and 2

2.  4 and 1

3.  259 and 1

4.  260 and 1

4

259 and 1

Explanation :
No Explanation available for this question

1.  XRI 0HF

2.  ANI F0H

3.  XRI F0H

4.  ANI 0FH.

4