# Consider the following logic circuit consisting of 2-4 decoder for each of decoder f0=1 when i1=0, i2=0 f1=1 when i1=1, i2=0 And so on, Which of the following gives value of g(x, y, z)

1.

2.  x.y.z

3.

4.  1.

4

1.

Explanation :
No Explanation available for this question

# The combinational logic circuit shown in the given figure has an output Q which is

1.  ABC

2.  A+B+C

3.

4.

4

A+B+C

Explanation :
No Explanation available for this question

# Digital multiplexer is basically a combinational logic circuit to perform the operation

1.  AND-AND

2.  OR-OR

3.  AND-OR

4.  OR-AND.

4

AND-OR

Explanation :
No Explanation available for this question

# The logic realized by the circuit shown in the figure below, is

1.

2.

3.

4.

4 Explanation :
No Explanation available for this question

# In the time division multiplexing

1.  Time is doubled between bits of a byte

2.  Time slicing at CPU level takes place

3.  Total time available in the channel is divided between several users and each users is allocated a time slice

4.  None of these.

4

Total time available in the channel is divided between several users and each users is allocated a time slice

Explanation :
No Explanation available for this question

# The output f of the 4-to-1 MUX shown in the given figure is

1.

2.  X+y

3.

4.

4

X+y

Explanation :
No Explanation available for this question

# In the figure shows a 4 to 1 MUX to be used to implement the sum S of a 1-bit full adder with input bits P and Q and the carry input Cin. Which of the following combinations of inputs to I0, I1, I2 and I3 of the MUX will realize the sum S

1.

2.

3.

4.

4 Explanation :
No Explanation available for this question

# In TTL circuit shown in the given figure, S2 to S0 are select line and X7 to X0 are input lines S0 and X0 are LSB’s the output is

1.  In determine

2.

3.

4.

4 Explanation :
No Explanation available for this question

# The output F of the multiplexer circuit shown in the given figure can be represented by

1.

2.

3.

4.

4 Explanation :
No Explanation available for this question

# A sequential multiplexer is connected as shown in the figure. Each time the multiplexer receivers the clock, it switches to the next cannel (from 6 it goes to 1) if input signals are

1.

2.

3.

4.

4 