# The circuit show in the figure given below

1.  Is an oscillating circuit and its output is a square wave

2.  Is one whose output remains stable in ‘1’ state

3.  Is one having output remains stable ‘0’ state

4.  Having a single pulse of 3 times propagation delay.

4

Is an oscillating circuit and its output is a square wave

Explanation :
No Explanation available for this question

# A latch is to be defined inputs L and M (an L M latch) the table specifying the desired next state at a clock pulse is given in below: L M Q Q+ 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 0 The expression for the next state Q+ is

1.  M + MQ

2.  L + LQ

3.  M + M

4.  L + L

4

L + L Explanation :
No Explanation available for this question

# The circuit in the figure converts

1.  BCD to binary code

2.  Binary to excess-3 code

3.  Excess-3 to gray code

4.  Gray to binary code.

4

BCD to binary code

Explanation :
No Explanation available for this question

# A sequential circuit using D flip-flop and logic gates is shown in the figure where X and Y are the inputs and Z is the output. The circuit is

1.  S-R FF with inputs X=R and Y=S

2.  S-R FF with inputs X=S and Y=R

3.  J-K FF with inputs X=J and Y=K

4.  J-K FF with inputs X=K and Y=J.

4

J-K FF with inputs X=K and Y=J.

Explanation :
No Explanation available for this question

# The digital block in the figure realized using two positive edge triggered D- flip flop. Assume that for t

1.

2.

3.

4.

4 Explanation :
No Explanation available for this question

# The circuit shown in the figure

1.  Is MOD -2 counter

2.  Is MOD -3 counter

3.  Generate sequence 00, 10, 01, 00……

4.  Generate sequence 00, 10, 00, 10, 00……

4

Is MOD -3 counter

Explanation :
No Explanation available for this question

# The mod-number of the asynchronous counter shown in the figure is

1.  24

2.  48

3.  25

4.  36.

4

24

Explanation :
No Explanation available for this question

# The three-stage Johnson counter as shown in figure is clocked at a constant frequency from the starting state of Q2Q1Q0=101. The frequency of output Q2Q1Q0 will be

1.

2.

3.

4.

4 Explanation :
No Explanation available for this question

# A 4-bit ripple counter and a 4-bit synchronous counter are made by fli-flops having a propagation delay of 10 ns each. if worst-case delay in the ripple counter and the synchronous counter be R and S respectively, then

1.  R=10 ns, S=40 ns

2.  R=40 ns, S=10 ns

3.  R=10 ns, S=30 ns

4.  R=30 ns, S=10 ns.

4

R=40 ns, S=10 ns

Explanation :
No Explanation available for this question

1.  10MHz

2.  10 MHz

3.  4 MHz

4.  20 MHz

4