It is desired to generate the following three Boolean functions: by using an OR gate array s shown in the figure where P1 and P5 are product terms in one or more of the variable a, The terms P1, P2, P3, P4 and P5are

1.  

2.  

3.  

4.  All of these.

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4
Correct Answer :


Explanation :
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The output of the circuit will be

1.  

2.  

3.  

4.  

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4
Correct Answer :


Explanation :
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To realize the given truth table from the circuit shown in the figure, the input to J in terms of A and B would have to be

1.  AB

2.  A

3.  B

4.  A

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4
Correct Answer :

B


Explanation :
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The circuit given in the figure id to be used to implement the function What values should be selected for I and J

1.  I=0 J=B

2.  I=1 J=B

3.  I=B J=1

4.  I=J=0.

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4
Correct Answer :

I=1 J=B


Explanation :
No Explanation available for this question

In a JK flip-flop we have and K=1. Assuming the flip-flop was initially cleared and then clocked for 6 pulses, the sequence at the Q, then clock for 6 pulses, the sequence at the Q output will be

1.  010000

2.  011001

3.  010010

4.  010101.

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4
Correct Answer :

010101.


Explanation :
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The characteristic equation of the T-FF is given by

1.  

2.  

3.  

4.  

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4
Correct Answer :


Explanation :
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A pulse train with a frequency of 1 MHz is counter using a modulo 1024 ripple-counter built with J-K flip-flops. For proper operation of the counter. The maximum permissible propagation delay per flip-flop stage is

1.  100 n sec

2.  50 n sec

3.  20 n sec

4.  10 n sec.

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4
Correct Answer :

100 n sec


Explanation :
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What is the frequency of the pulses at the points a, b, c, d in the circuit shown

1.  10 kHz 500Hz 31.25 Hz 3.9 Hz

2.  20 kHz 510Hz 32 Hz 4 Hz

3.  15 kHz 500Hz 30 Hz 4 Hz

4.  10 kHz 520Hz 50 Hz 5 Hz.

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4
Correct Answer :

10 kHz 500Hz 31.25 Hz 3.9 Hz


Explanation :
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In a 4-bit counter, the outputs of 3 JK FFs from MSB downward are connected to the NAND gate whose output is connected to CLR

1.  It is a MOD-14 counter

2.  It is a MOD-13 counter

3.  It is a divide by-13 counter

4.  It is a divide by-14 counter.

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4
Correct Answer :

It is a divide by-14 counter.


Explanation :
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The state transition given below is realized by clocked JK FF state transition Qn Qn+1 0 0 0 1 1 0 1 1 The JK input to realize the transition is

1.  J K 0 Ø 1 Ø Ø 1 Ø 0

2.  J K Ø 0 Ø 1 1 Ø 0 Ø

3.  J K 0 Ø Ø 0 Ø 1 1 Ø

4.  J K 1 Ø Ø 0 0 Ø Ø 1

View Answer  
4
Correct Answer :

J K

1 Ø

Ø 0

0 Ø

Ø 1


Explanation :
No Explanation available for this question
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