1. continues its normal operations
2. suspends its normal operations
3. needs to initiate read (write) command
4. needs to check if the input/output device is ready for data transfer
continues its normal operations
1. a DI instruction
2. a system reset
3. acknowledgement of a previous interrupt
4. none of these
none of these
1. all the registers of the CPU are being reset
2. all the registers and counters are being reset
3. all the registers and counters are being reset and in addition this signal can be used to reset external support chips
4. processing can begin when this signal goes high
all the registers and counters are being reset and in addition this signal can be used to reset external support chips
1. Fetch and Halt states
2. Fetch and Interrupt states
3. Fetch and Execute states
4. Halt and Execute states
Fetch and Execute states
1. Halt state
2. Fetch state
3. Execute state
4. Interrupt state
Fetch state
1. the delay between application of proper chip select signal and the stable output address
2. the delay between the previous valid output data and the next change in address
3. the time for which the output data remains valid when the device is no longer selected
4. maximum time for which the valid address can be changed
the delay between application of proper chip select signal and the stable output address
1. execute
2. fetch
3. interrupt
4. none of these
fetch
1. 60H to 63 H
2. A 4 to A 7 H
3. 71H to 73 H
4. 70 H to 73 H
60H to 63 H
1. stops execution of instructions
2. acknowledges interrupt and branches to a subroutine
3. acknowledges interrupt and continues
4. acknowledges interrupt and waits for the next instruction from the interrupting device
acknowledges interrupt and branches to a subroutine
1. assembly of processor in a production line
2. creation of new programmes using different modules
3. translation of a program from assembly language to machine language
4. translation of a higher level language into English text
translation of a program from assembly language to machine language