# A TTL NOT gate circuit is shown in figure. Assuming VBE = 0.7 V of both the transistors, if Vi = 3.0 V, then the states of the two transistors will be

1.  Q1 ON and Q2 OFF

2.  Q1 reverse ON and Q2 OFF

3.  Q1 reverse ON and Q2 ON

4.  Q1 OFF ans Q2 reverse ON

4

Q1 reverse ON and Q2 ON

Explanation :
No Explanation available for this question

# A student has made a 3-bit binary down counter and connected to the R-2R ladder type DAC [Gain = (-1 K/2R)] as shown in figure to generate a staircase waveform. The output achieved is different as shown in figure. What could be the possible cause of this error ?

1.  The resistance values are incorrect

2.  The counter is not working properly

3.  The connection from the counter to DAC is not proper

4.  The R and 2R resistances are interchanged

4

The connection from the counter to DAC is not proper

Explanation :
No Explanation available for this question

# A 4 × 1 MUX is used to implement a 3-input Boolean function as shown in figure. The Boolean function F (A, B, C) implemented is

1.  F (A, B, C) = Σ(1, 2, 4, 6)

2.  F (A, B, C) = Σ(1, 2, 6)

3.  F (A, B, C) = Σ(2, 4, 5, 6)

4.  F (A, B, C) = Σ(1, 5, 6)

4

F (A, B, C) = Σ(1, 2, 4, 6)

Explanation :
No Explanation available for this question

# A software delay subroutine is written as given below:  DELAY :MVI H,255 D  MVI L,255 D         LOOP:DCR L       JNZ  LOOP                    DCR H                  JNZ  LOOP                   How many times DCR L instruction will be executed

1.  255

2.  510

3.  65025

4.  65279

4

255

Explanation :
No Explanation available for this question

# In an 8085 A microprocessor based system, it is desired to increment the contents of memory location whose address is available in (D, E) register pair and store the result in same location. The sequence of instructions is

1.  XCHG INR M

2.  XCHG INX H

3.  INX D XCHG

4.  INR M XCHG

4

XCHG

INR M

Explanation :
No Explanation available for this question

# A single-phase inverter is operated in PWM mode generating a single-pulse of width 2d in the centre of each half cycle as shown in figure. It is found that the output voltage is free from 5th harmonic for pulse width 144°. What will be percentage of 3rd harmonic present in the output voltage (V03/V01 max)

1.  0.0%

2.  19.6%

3.  31.7%

4.  53.9%

4

19.6\%

Explanation :
No Explanation available for this question

# A 3-phase fully controlled bridge converter with free wheeling diode is fed from 400 V, 50 Hz AC source and is operating at a firing angle of 60°. The load current is assumed constant at 10 A due to high load inductance. The input displacement factor (IDF) and the input power factor (IPF) of the converter will be

1.  IDF = 0.867;IPF = 0.828

2.  IDF = 0.867;IPF = 0.552

3.  IDF = 0.5;IPF = 0.478

4.  IDF = 0.5;IPF =0.318

4

IDF = 0.5;IPF = 0.478

Explanation :
No Explanation available for this question

# A voltage commutation circuit is shown in figure. If the turn off time of the SCRs is 50 µ sec and a safety margin of 2 is considered, then what will be the approximate minimum value of capacitor required for proper commutation

1.  2.88 µF

2.  1.44 µF

3.  0.91 µF

4.  0.72 µF

4

2.88 µF

Explanation :
No Explanation available for this question

# A solar cell of 350 V is feeding power to an ac supply of 440 V, 50 Hz through a 3-phase fully controlled bridge converter. A large inductance is connected in the dc circuit to maintain the dc current at 20 A. If the solar cell resistance is 0.5 , then each thyristor will be reverse biased for a period of

1.  125°

2.  120°

3.  60°

4.  55°

4

125°

Explanation :
No Explanation available for this question

1.  23.8.A

2.  15 A

3.  11.9 A

4.  3.54 A

4