1. Number of instruction s in the current program that have already been executed
2. Total number of instructions in the program being executed
3. Memory address of the instruction that is being currently executed
4. Memory address of the instruction that is to be executed next.
Memory address of the instruction that is to be executed next.
1. 1
2. 2
3. 3
4. 4
3
1. TRAP
2. INTR
3. RST7.5
4. RST3
RST3
1. -256
2. -255
3. -128
4. -127
-128
1. Make the processor wait during a DMA operation
2. Make the processor wait during a power interrupt processing
3. Make the processor wait during a power shutdown
4. Interface slow peripherals to the processor
Interface slow peripherals to the processor
1. PROM contains a programmable AND array and a fixed OR array
2. PLA contains a fixed AND array and a programmable OR array
3. PROM contains a fixed AND array and programmable OR array
4. None of these
PROM contains a fixed AND array and programmable OR array
1. SP=27 FF,HL=1003
2. SP=27 FD,HL=1003
3. SP=27 FF,HL=1006
4. SP=27 FD,HL=1006
SP=27 FD,HL=1006
1. I/O devices have 8-bit addresses
2. I/O devices are accessed using IN and OUT instructions
3. There can be a maximum of 256 input devices and 256 output devices
4. Arithmetic and logic operations can be directly performed with the I/O data
Arithmetic and logic operations can be directly performed with the I/O data
1. 5 and 2
2. 4 and 1
3. 259 and 1
4. 260 and 1
259 and 1
1. Carry status flag
2. Auxiliary carry ststus flag
3. Sign status flag
4. Zero status flag
Sign status flag