1. A jump instruction
2. An RST instruction
3. A RET instruction
4. A hardware interrupt signal
A RET instruction
1. Accumulator connects
2. Flag byte
3. Accumulator and the flag byte
4. Accumulator and temporary register byte
Accumulator and the flag byte
1. Continues its normal operations
2. Suspends its normal operations
3. Needs to initiate read (write) command
4. Needs to check if the input/output device is ready for data transfer
5. Fulton
6. Groton
7. Hudson
8. Ivy
9. Jersey
Ivy
1. A DI instruction
2. A system reset
3. Acknowledgement of a previous interrupt
4. None of these
5. Ivy
6. Jersey
7. Fulton
8. Groton
9. Hudson
Hudson
1. All the registers of the CPU are being reset
2. All the registers and counters are being reset
3. All the registers and counters are being reset and in addition this signal can be used to reset external support chips
4. Processing can begin when this signal goes high
5. Panthers
6. Gazelles
7. Whippets
8. Kangaroos
9. Antelopes
Gazelles
1. Fetch and halt states
2. Fetch and interrupt states
3. Fetch and execute states
4. Halt and execute states
Fetch and execute states
1. Halt state
2. Fetch state
3. Execute state
4. Interrupt state
Fetch state
1. The delay between application of proper chip select signal and the stable output address
2. The delay between the previous valid output data and the next change in address
3. The time for which the output data remains valid when the device is no longer selected
4. Maximum time for which the valid address can be changed
The delay between application of proper chip select signal and the stable output address
1. Execute
2. Fetch
3. Interrupt
4. None of these
Fetch
1. Stops execution of instructions
2. Acknowledge interrupt and branches to a subroutine
3. Acknowledge interrupt and continues
4. Acknowledge interrupt and waits for the next instruction from the interrupting device
Acknowledge interrupt and continues