1. IO/M
2. Status signals
3. ALE
4. HOLD and HLDA
ALE
1. IO/M
2. READY
3. HOLD and HLDA
4. RD and WR
HOLD and HLDA
1. Store address of the next instruction to be executed
2. Store temporary data to be used in arithmetic operaions
3. Store the status of the microprocess
4. None of these
Store address of the next instruction to be executed
1. ALE signal
2. HOLD signal
3. READY signal
4. None of these
READY signal
1. Accumulator contents
2. Flags
3. Both accumulator and flag
4. Status bits
Both accumulator and flag
1. Number of address lines
2. Number of data lines
3. Instruction set
4. Instruction set and operating frequency
Instruction set and operating frequency
1. Speed
2. Directly addressable memory
3. Data handling capability
4. All of these
All of these
1. To give slow devices additional time to put out valid data
2. To insert a deliberate delay
3. During I/O operation
4. None of these
To give slow devices additional time to put out valid data
1. Number of address lines
2. Number of data lines
3. Operating frequency
4. All of these
All of these
1. Allow the memory capacity to be 1 megabyte even though the addresses associated with the individual instructions are only 16 bits wide
2. Allow the instruction, data or stack portion of a program to be more than 64K bytes long by using more than one code, data or stack segment
3. Facilitate the use of separate memory area for a program, its data and the stack
4. All of these
All of these